ISL58328
12
FN6329.2
July 29, 2013
Serial Interface Protocol
WRITING CYCLE INTO ISL58328
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
A4
A5
A6
0
t
CDS
t
CDH
t
CC
tCH
t
CL
t
ERSR
SEN
SCLK
SDATA
t
SREF
R/W BIT, ADDRESS BITS, AND DATA BITS ARE CLOCKED INTO ISL58328 AT RISING EDGE OF SCLK.
R/W
READING CYCLE FROM ISL58328
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
A4
A5
A6
1
t
CDS
t
CDH
t
CC
t
CH
t
CL
t
ERSR
SEN
SCLK
SDATA
t
SREF
Hi-Z
t
CDD
R/W BIT AND ADDRESS BITS ARE CLOCKED INTO ISL58328 AT RISING EDGE OF SCLK.
DATA BITS ARE CLOCKED OUT FROM ISL58328 AT FALLING EDGE OF SCLK.
THE LAST BIT (D0) OF DATA IS CLOCKED BY THE FALLING EDGE OF SEN.
t
EH
t
EH
t
EL
t
EL
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